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d a t a sh eet preliminary speci?cation supersedes data of 1999 oct 12 file under integrated circuits, ic01 2000 jan 04 integrated circuits UDA1328T multi-channel filter dac
2000 jan 04 2 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T contents 1 features 1.1 general 1.2 multiple format input interface 1.3 multi-channel dac 1.4 advanced audio configuration 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 system clock 8.2 application modes 8.3 interpolation filter (dac) 8.4 digital silence detection 8.5 noise shaper 8.6 filter stream dac 8.7 static mode 8.7.1 system clock setting 8.7.2 de-emphasis control 8.7.3 digital interface formats 8.8 l3 mode 8.8.1 digital interface formats 8.8.2 l3 address 9 l3 interface description 9.1 address mode 9.2 data transfer mode 9.2.1 programming the sound processing and other features 9.2.2 reset bit 9.2.3 system clock frequency 9.2.4 data input format 9.2.5 quick mute 9.2.6 power control 9.3 feature settings 9.3.1 volume control 9.3.2 sub volume control 9.3.3 mute 9.3.4 digital silence mode 9.3.5 de-emphasis 9.3.6 output polarity control 10 limiting values 11 handling 12 thermal characteristics 13 quality specification 14 dc characteristics 15 ac characteristics (analog) 16 ac characteristics (digital) 17 application information 18 package outline 19 soldering 19.1 introduction to soldering surface mount packages 19.2 reflow soldering 19.3 wave soldering 19.4 manual soldering 19.5 suitability of surface mount ic packages for wave and reflow soldering methods 20 definitions 21 life support applications
2000 jan 04 3 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 1 features 1.1 general 2.7 to 3.6 v power supply 5 v tolerant ttl compatible inputs selectable control via l3 microcontroller interface or via static pin control multi-channel integrated digital filter plus non-inverting digital-to-analog converter (dac) supports sample frequencies between 5 and 100 khz digital silence detection (output) slave mode only applications no analog post filtering required for dac easy application. 1.2 multiple format input interface i 2 s-bus, msb-justified and lsb-justified format compatible (in l3 mode) i 2 s-bus and lsb-justified format compatible 1f s input format data rate. 1.3 multi-channel dac 6-channel dac with power on/off control digital logarithmic volume control via l3; volume can be set for each of the channels individually digital de-emphasis for 32, 44.1, 48 and 96 khz f s via l3 and, for 32, 44.1 and 48 khz in static mode soft or quick mute via l3 output signal polarity control via l3 microcontroller interface. 1.4 advanced audio con?guration 6-channel line output (under l3 volume control) a stereo differential output (channel 1 and channel 2) for improved performance high linearity, wide dynamic range, low distortion. 2 applications this multi-channel dac is eminently suitable for dvd like applications in which 5.1 channel encoded signals are used. 3 general description the uda1328 is a single-chip 6-channel dac employing bitstream conversion techniques, which can be used either in l3 microcontroller mode or in static pin mode. the uda1328 supports the i 2 s-bus data format with word lengths of up to 24 bits, the msb-justified data format with word lengths of up to 24 bits and the lsb-justified serial data format with word lengths of 16, 18, 20 and 24 bits. all digital sound processing features can be controlled with the l3 interface e.g. volume control, selecting digital silence type, output polarity control and mute. also system features such as power control, digital silence detection mode and output polarity control. under static pin control, via static pins, the system clock can be set to either 256f s or 384f s support, digital de-emphasis can be set, there is digital mute and the digital input formats can also be set. 4 ordering information type number package name description version UDA1328T so32 plastic small outline package; 32 leads; body width 7.5 mm sot287-1
2000 jan 04 4 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 5 quick reference data notes 1. the output voltage scales proportionally with the power supply voltage. 2. in this case the two outputs per channel (for channels 1 and 2) are combined. symbol parameter conditions min. typ. max. unit supplies v dda analog supply voltage 2.7 3.3 3.6 v v ddd digital supply voltage 2.7 3.3 3.6 v i dda analog supply current 6 channels active - 28 - ma i ddd digital supply current - 11 - ma t amb ambient temperature - 40 - +85 c dac: channels 1 and 2 differential v o(rms) output voltage (rms value) notes 1 and 2 - 2 - v (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db f s =48khz -- 95 - 88 db f s =96khz -- 90 - db at - 60 db; a-weighted f s =48khz -- 46 - db f s =96khz -- 44 - db s/n signal-to-noise ratio code = 0; a-weighted f s =48khz - 106 - db f s =96khz - 104 - db dac: channels 3 to 6 (channels 1 and 2 non-differential) v o(rms) output voltage (rms value) note 1 - 1 - v (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db f s =48khz -- 90 - 83 db f s =96khz -- 85 - db at - 60 db; a-weighted f s =48khz -- 43 - db f s =96khz -- 41 - db s/n signal-to-noise ratio code = 0; a-weighted f s =48khz - 103 - db f s =96khz - 101 - db a cs channel separation - 100 - db
2000 jan 04 5 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 6 block diagram fig.1 block diagram. handbook, full pagewidth mgr979 static 9 ds 26 mute 23 deem1 24 deem0 25 18 19 17 10 11 12 13 14 test3 8 test2 22 test1 27 vout3 1 4 sysclk 16 control interface digital interface volume/mute/de-emphasis UDA1328T dac interpolation filter 6-channel noise shaper dac dac dac dac dac vout1n 29 6 vout1p 28 vout5 vout4 2 5 vout2n 31 vout2p 32 vout6 v dda 7, 15 n.c. 3 v ssa 30 v ref 21 20 bck ws datai12 datai34 datai56 l3data l3clock l3mode v ddd v ssd
2000 jan 04 6 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 7 pinning symbol pin description vout3 1 channel 3 analog output vout4 2 channel 4 analog output v ssa 3 analog ground vout5 4 channel 5 analog output vout6 5 channel 6 analog output v dda 6 analog supply voltage n.c. 7 not connected (reserved) test3 8 test output 3 static 9 static mode/l3 mode switch input bck 10 bit clock input ws 11 word select input datai12 12 data input channel 1 and 2 datai34 13 data input channel 3 and 4 datai56 14 data input channel 5 and 6 n.c. 15 not connected (reserved) sysclk 16 system clock: 256f s , 384f s , 512f s and 768f s l3mode 17 l3 mode selection input l3clock 18 l3 clock input l3data 19 l3 data input v ssd 20 digital ground v ddd 21 digital supply voltage test2 22 test output 2 mute 23 static mute control input deem1 24 deem control 1 input (static mode) deem0 25 l3 address select (l3 mode)/deem control 0 input (static mode) ds 26 digital silence detect output test1 27 test input 1 vout1p 28 channel 1 analog output p vout1n 29 channel 1 analog output n v ref 30 dac reference voltage vout2n 31 channel 2 analog output n vout2p 32 channel 2 analog output p fig.2 pin configuration. handbook, halfpage UDA1328T mgr980 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vout3 vout4 v ssa vout5 vout6 v dda n.c. test3 static bck ws datai12 datai34 datai56 vout2p vout2n v ref vout1n test1 ds vout1p deem0 deem1 mute test2 v ddd v ssd l3data n.c. sysclk l3clock l3mode
2000 jan 04 7 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 8 functional description 8.1 system clock the uda1328 operates in slave mode only, this means that in all applications the system must provide the system clock. the system frequency is selectable. the options are 256f s , 384f s , 512f s and 768f s for the l3 mode and 256f s or 384f s for the static mode. the system clock must be frequency-locked to the digital interface signals. it should be noted that the uda1328 can operate from 5 to 100 khz sampling frequency (f s ). however in 768f s mode the sampling frequency must be limited to 55 khz. 8.2 application modes operating mode can be set with the static pin, either to l3 mode (static = low) or to the static mode (static = high). see table 1 for pin functions in the static mode. table 1 mode selection in the static mode notes 1. sf1 and sf0 are the serial format inputs (2-bit). 2. x means that the pin has no function in this mode and can best be connected to ground. 8.3 interpolation ?lter (dac) the digital filter interpolates from 1 to 128f s by cascading a half-band filter and a fir filter, see table 2. the overall filter characteristic of the digital filters is illustrated in fig.3, and the pass-band ripple is illustrated in fig.4. both figures are with a 44.1 khz sampling frequency. table 2 interpolation ?lter characteristics 8.4 digital silence detection the uda1328 can detect digital silence conditions in channels 1 to 6, and report this via the output pin ds. this function is implemented to allow for external manipulation of the audio signal in the absence of program material, such as muting or recorder control. an active low output is produced at the ds pin if the channels selected via l3 or for all channels in static mode, carries all zeroes for at least 9600 consecutive audio samples (equals 200 ms for f s = 48 khz). the ds pin is also active low when the output is digitally muted either via the l3 interface or via the static pin. in static mode all channels participate in the digital silence detection. in l3 mode control each channel can be set, either to participate in the digital silence detection or not. 8.5 noise shaper the 3rd-order noise shaper operates at 128f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using a filter stream dac (fsdac). 8.6 filter stream dac the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. no post-filter is needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac scales proportionally with the power supply voltage. 8.7 static mode the uda1328 is set to static mode by setting the static pin high. the function of 6 pins of the device now get another function as can be seen in table 1. 8.7.1 s ystem clock setting in static mode pin 18 (l3clock) is used to select the system clock setting. when pin 18 is low, the device is in 256f s mode, when pin 18 is high the device is in 384f s mode. pin l3 mode static mode l3clock l3clock clock select l3mode l3mode sf1 (1) l3data l3data sf0 (1) mute x (2) mute deem1 x (2) deem1 deem0 l3adr deem0 item condition value (db) pass-band ripple 0 to 0.45f s 0.02 stop band >0.55f s - 55 dynamic range 0 to 0.45f s >114 dc gain -- 3.5
2000 jan 04 8 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 8.7.2 d e - emphasis control in static pin mode the pins deem0 and deem1 control the de-emphasis mode; see table 3. table 3 de-emphasis control 8.7.3 d igital interface formats in static pin mode the digital audio interface formats can be selected via pin 17 (sf1) and 19 (sf0). the following interface formats can be selected (see also table 4): i 2 s-bus with data word length of up to 24 bits lsb-justified format with data word length of 16, 20 or 24 bits. table 4 input format selection in the static mode it should be noted that the digital audio interface holds that the bck frequency can be 64 times the ws maximum frequency, or f bck 64 f ws deem mode deem1 deem0 no de-emphasis 0 0 32 khz de-emphasis 0 1 44.1 khz de-emphasis 1 0 48 khz de-emphasis 1 1 input format sf1 sf0 i 2 s-bus 0 0 lsb-justi?ed 16 bits 0 1 lsb-justi?ed 20 bits 1 0 lsb-justi?ed 24 bits 1 1 8.8 l3 mode the device is set to l3 mode by setting the static pin to low. the device can then be controlled via the l3 microcontroller interface (see chapter 9). 8.8.1 d igital interface formats the following interface formats can be selected in the l3 mode: i 2 s-bus with data word length of up to 24 bits msb-justified with data word length of up to 24 bits lsb-justified format with data word length of 16, 18, 20 or 24 bits. 8.8.2 l3 address the uda1328 can be addressed via the l3 microcontroller interface using one of two addresses. this is done in order to individually control the uda1328 and other philips dacs or codecs via the same l3 bus. the address can be selected using pin 25 (deem0) in l3 mode. when pin 25 is set low, the address is 000100. when pin 25 is set high the address is 000101.
2000 jan 04 9 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T fig.3 overall frequency characteristics. f s = 6.14400 mhz handbook, halfpage 0 200 0 - 100 - 80 mgr981 - 60 - 40 - 20 40 80 120 160 volume (db) f (khz) fig.4 pass-band ripple of all filters. f s = 6.14400 mhz handbook, halfpage 0 102030 - 3.45 - 3.47 - 3.49 - 3.51 - 3.53 mgr982 v o (db) f (khz)
2000 jan 04 10 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... a ndbook, full pagewidth mgr751 16 b5 b6 b7 b8 b9 b10 left lsb justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 b3 b4 b5 b6 left lsb justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 left lsb justified format 18 bits ws bck data right 15 18 17 2 1 msb b2 b3 b4 b17 lsb 16 15 18 17 2 1 b17 lsb 16 msb b2 left lsb justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb msb b2 2 1 > = 8 12 3 left input format i 2 s ws bck data right 3 > = 8 msb b2 fig.5 serial interface; input formats.
2000 jan 04 11 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 9 l3 interface description the following system and digital sound processing features can be controlled in the microcontroller mode of the uda1328: data input format de-emphasis for 32, 44.1, 48 and 96 khz volume control: master and for individual channels soft or quick mute: master and for individual channels output polarity control: master and for individual channels digital silence control: master and for individual channels power-down mode. the exchange of data and control information between the microcontroller and the uda1328 is accomplished via a serial hardware interface comprising the following pins: l3data: microcontroller interface data line l3mode: microcontroller interface mode line l3clock: microcontroller interface clock line. information transfer via the microcontroller bus is organized lsb first and is in accordance with the so called l3 format, in which two different modes of operation can be distinguished. the address mode and data transfer mode are illustrated in figs 6 and 7. the address mode is required to select a device communicating via the l3-bus and to define the destination registers for the data transfer mode. data transfer for the uda1328 can only be in one direction; input to the uda1328 to program its sound processing and other functional features. 9.1 address mode the address mode is used to select a device for subsequent data transfer and to define the destination registers. the address mode is characterized by l3mode being low and a burst of 8 pulses on l3clock, accompanied by 8 data bits. the fundamental timing is shown in fig.6. data bits 0 and 1 indicate the type of subsequent data transfer as given in table 5. table 5 selection of data transfer data bits 7 to 2 represent a 6-bit device address, with bit 7 being the msb and bit 2 the lsb. the address of the uda1328 is 000100 (bit 7 to bit 2) when l3adr (deem0) = low or 000101 when l3adr = high. in the event that the uda1328 receives a different address, it will deselect its microcontroller interface logic. 9.2 data transfer mode the selection preformed in the address mode remains active during subsequent data transfers, until the uda1328 receives a new address command. the fundamental timing of data transfers is essentially the same as in the address mode, shown in fig.6. the maximum input clock and data rate is 64f s . all transfers are byte wise, i.e. they are based on groups of 8 bits. data will be stored in the uda1328 after the eighth bit of a byte has been received. a multibyte transfer is illustrated in fig.8. 9.2.1 p rogramming the sound processing and other features the sound processing and other feature values are stored in independent registers. the first selection of the registers is achieved by the choice of data type that is transferred. this is performed in the address mode, bit 1 and bit 0 (see table 5). the second selection is performed by the 2 msbs of the data byte (bit 7 and bit 6). the other bits in the data byte (bit 5 to bit 0) is the value that is placed in the selected registers. when the data transfer of type data is selected, the features volume, sub volume, de-emphasis, mute, digital silence settings, output polarity control and channel selection can be controlled. when the data transfer of type status is selected, the features system clock frequency, data input format, mute mode and power control can be controlled. bit 1 bit 0 transfer 0 0 data (volume, de-emphasis, mute, digital silence mode, polarity control) 0 1 not used 1 0 status (system clock frequency, data input format, mute mode, power control) 1 1 not used
2000 jan 04 12 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T fig.6 timing address mode. handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a handbook, full pagewidth t stp(l3) t stp(l3) t su(l3)d t su(l3)da t h(l3)da t h(l3)d mgl882 t cy(clk)l3 l3mode l3clock t clk(l3)h t clk(l3)l bit 0 l3data write bit 7 fig.7 timing for data transfer mode.
2000 jan 04 13 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T table 6 data transfer of type status table 7 data transfer of type data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register selected 0 rst sc1 sc0 if2 if1 if0 0 reset system clock frequency (1 and 0) data input format (2 to 0) 100000qmpc quick/soft mute power control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register selected 0 0 vc5 vc4 vc3 vc2 vc1 vc0 volume control (5 to 0) 010000vq1vq0 0.25 db step sub volume (1 and 0) 1 0 de2 de1 de0 mt dsm plc de-emphasis (2 to 0) mute digital silence mode polarity control 1100achch2ch1ch0 all channels select channel select (2 to 0) fig.8 multibyte transfer. handbook, full pagewidth t stp(l3) address l3data l3clock l3mode address data byte #1 data byte #2 mgl725
2000 jan 04 14 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 9.2.2 r eset bit a 1-bit value to initialize the l3 registers with the default settings (except the system clock setting and the data input format setting) by writing a logic 1 to rst (see table 6). the default settings after reset are as follows: mute mode: soft mute power: on volume: 0 db sub volume: 0 db de-emphasis: off mute: off silence detect mode: detect polarity: non-inverting. 9.2.3 s ystem clock frequency a 2-bit value (sc1 and sc0) to select the used external clock frequency (see table 8). table 8 system clock frequency settings 9.2.4 d ata input format a 3-bit value (if2 to if0) to select the used data format (see table 9). table 9 data input format settings sc1 sc0 function 0 0 512f s 0 1 384f s 1 0 256f s 1 1 768f s if2 if1 if0 function 000i 2 s-bus 0 0 1 lsb-justi?ed; 16 bits 0 1 0 lsb-justi?ed; 18 bits 0 1 1 lsb-justi?ed; 20 bits 1 0 0 msb-justi?ed 1 0 1 lsb-justi?ed; 24 bits 1 1 0 reserved 1 1 1 reserved 9.2.5 q uick mute a 1-bit value to set the mute mode to either soft mute (via cosine roll-off), quick or hard mute. table 10 quick mute 9.2.6 p ower control a 1-bit value to disable the adc and/or dac to reduce power consumption. table 11 power control settings 9.3 feature settings in the uda1328 there are features that can be controlled either per-channel or all at the same time. these features are: volume control sub volume control mute output polarity control digital silence detect. when a per-channel setting is required for these features, the ach bit (see table 7) must be set to logic 0 before writing a new value to one of the features. once this has been performed a channel is selected via the ch2 to ch0 bits. the features for this channel can be controlled without sending the same channel address again (low microcontroller mode). when the ach bit is set to logic 1, which means all channels select, all channels will be set to the same value of the feature sent afterwards. for the digital silence detector it holds that the ds pin is either active on the selected channel when bit ach is set to logic 0 before writing the dsm bit, or the ds pin is active on all channels when the ach bit is set to logic 1. qm function 0 soft mute mode 1 quick mute mode pc function 0 all channels off 1 all channels on
2000 jan 04 15 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 9.3.1 c hannel selection mode a 1-bit value to set the selection mode (either individually or per-channel) for the volume, mute, polarity control and silence detect is given in table 12. the 3-bit value is given in table 13. table 12 1-bit selection note 1. for setting the de-emphasis mode, the ach bit must be set to logic 1 before setting the de-emphasis. table 13 3-bit selection 9.3.2 v olume control a 6-bit value to program the channel volume attenuation (vc5 to vc0). the range is 0 db to - db in steps of 1 db (see table 14). table 14 volume settings ach (1) function 0 individual channel select; use ch(2 : 0) 1 all channels selected ch2 ch1 ch0 function 0 0 0 channel 1 selected 0 0 1 channel 2 selected 0 1 0 channel 3 selected 0 1 1 channel 4 selected 1 0 0 channel 5 selected 1 0 1 channel 6 selected 1 1 0 not used 1 1 1 not used vc5 vc4 vc3 vc2 vc1 vc0 volume (db) 000000 0 000001 0 000010 - 1 000011 - 2 :::::: : 111011 - 58 111100 - 59 111101 - 60 111110 - 111111 - 9.3.3 s ub volume control a 2-bit value to program the channel volume attenuation with a 0.25 db step (vq1 and vq0). to validate the sub volume settings in these registers, the volume control registers of corresponding channels must be updated one after the other. table 15 sub volume settings 9.3.4 m ute a 1-bit value to enable the digital mute (the type of mute is set via the qm bit in the status register). table 16 mute 9.3.5 d igital silence mode a 1-bit value to set the digital silence mode. this bit is set together with the channel address ch2 to ch0 and the ach bit. when the ach bit is set to logic 0, each channel can be selected for digital silence detection. when the ach bit is set to logic 1 all channels are selected. table 17 digital silence mode vq1 vq0 volume (db) 0 0 0.00 01 - 0.25 10 - 0.50 11 - 0.75 mt function 0 no muting 1 muting dsm function 0 no participation 1 participates
2000 jan 04 16 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 9.3.6 d e - emphasis a 2-bit value to enable the digital de-emphasis filter. table 18 de-emphasis settings 9.3.7 o utput polarity control a 1-bit value to program the output polarity of the output signal. this bit must be used together with the ch2 to ch0 bits and the ach bit to either select the polarity for all channels or to set for each channel individually. table 19 output polarity control de2 de1 de0 function 0 0 0 no de-emphasis 0 0 1 de-emphasis; 32 khz 0 1 0 de-emphasis; 44.1 khz 0 1 1 de-emphasis; 48 khz 1 0 0 de-emphasis; 96 khz plc function 0 non-inverting 1 inverting 10 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. all supply connections must be made to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor, expect pin 19 (l3data) which can withstand esd pulses of - 2500 to +2500 v. 3. equivalent to discharging a 200 pf capacitor via a 0.75 m h series inductor. 11 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. 12 thermal characteristics 13 quality specification in accordance with snw-fq-611-e . the number of the quality specification can be found in the quality reference handbook . symbol parameter conditions min. max. unit v ddd digital supply voltage note 1 - 5.0 v v dda analog supply voltage note 1 - 5.0 v t xtal(max) maximum crystal temperature - 150 c t stg storage temperature - 65 +125 c t amb ambient temperature - 40 +85 c v es electrostatic handling note 2 - 3000 +3000 v note 3 - 250 +250 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 58 k/w
2000 jan 04 17 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 14 dc characteristics v ddd =v dda = 3.3 v; t amb =25 c; r l =5k w . all voltages referenced to ground (pins 3 and 20); unless otherwise speci?ed. notes 1. all supply connections must be made to the same external power supply unit. 2. when the dac drives a capacitive load above 50 pf, a series resistor of 100 w must be used to prevent oscillations in the output operational amplifier. symbol parameter conditions min. typ. max. unit supplies v dda analog supply voltage note 1 2.7 3.3 3.6 v v ddd digital supply voltage note 1 2.7 3.3 3.6 v i dda analog supply current all channels active; operating mode - 28 - ma i ddd digital supply current operating mode - 11 - ma digital input pins: 5 v tolerant ttl compatible v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v v il(th) low-level threshold input voltage; falling edge 0.9 - 1.45 v v ih(th) high-level threshold input voltage; rising edge 1.4 - 1.9 v v hyst schmitt trigger hysteresis voltage 0.4 - 0.7 v ? i li ? input leakage current -- 1 m a c i input capacitance -- 10 pf digital output pin v oh high-level output voltage i oh = - 2 ma 0.85v ddd -- v v ol low-level output voltage i ol =2ma -- 0.4 v dac v ref reference voltage referenced to v ssa 0.45v dda 0.5v dda 0.55v dda v i o(max) maximum output current (thd + n)/s < 0.1% - 0.22 - ma r l load resistance 3 -- k w c l load capacitance note 2 -- 50 pf
2000 jan 04 18 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 15 ac characteristics (analog) v ddd =v dda = 3.3 v; f i = 1 khz; t amb =25 c; r l =5k w . all voltages referenced to ground (pins 3 and 20); unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit dac: channels 1 and 2 in differential mode v o(rms) output voltage (rms value) - 2 - v d v o unbalance between channels - 0.1 - db (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 48 khz; at 0 db -- 95 - 88 db f s = 48 khz; at - 60 db; a-weighted -- 46 - db f s = 96 khz; at 0 db -- 90 - db f s = 96 khz; at - 60 db; a-weighted -- 44 - db s/n signal-to-noise ratio f s = 48 khz; code = 0; a-weighted - 106 - db f s = 96 khz; code = 0; a-weighted - 104 - db dac: channels 3 to 6 v o(rms) output voltage (rms value) - 1 - v d v o unbalance between channels - 0.1 - db (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 48 khz; at 0 db -- 90 - 83 db f s = 48 khz; at - 60 db; a-weighted -- 43 - db f s = 96 khz; at 0 db -- 85 - db f s = 96 khz; at - 60 db; a-weighted -- 41 - db s/n signal-to-noise ratio f s = 48 khz; code = 0; a-weighted - 103 - db f s = 96 khz; code = 0; a-weighted - 101 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple(p-p) = 100 mv - 50 - db
2000 jan 04 19 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 16 ac characteristics (digital) v ddd =v dda = 2.7 to 3.6 v; t amb = - 20 to +85 c; r l =5k w . all voltages referenced to ground (pins 3 and 20); unless otherwise speci?ed. the typical timing is speci?ed at 44.1 khz sampling frequency. note 1. in the 768f s clock mode, the sampling frequency must be limited to 55 khz. symbol parameter conditions min. typ. max. unit t sys system clock cycle f sys = 256f s 35 88 780 ns f sys = 384f s 23 59 520 ns f sys = 512f s 20 44 390 ns f sys = 768f s ; note 1 20 30 260 ns t cwl low-level system clock pulse width f sys < 19.2 mhz 30 - 70 %t sys f sys 3 19.2 mhz 40 - 60 %t sys t cwh high-level system clock pulse width f sys < 19.2 mhz 30 - 70 %t sys f sys 3 19.2 mhz 40 - 60 %t sys t r rise time -- 20 ns t f fall time -- 20 ns serial input data timing (see fig.9) t cy(clk)(bit) bit clock period 140 -- ns t clkh(bit) bit clock high time 60 -- ns t clkl(bit) bit clock low time 60 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t su(i)(d) data input set-up time 20 -- ns t h(i)(d) data input hold time 0 -- ns t su(ws) word selection set-up time 20 -- ns t h(ws) word selection hold time 10 -- ns microcontroller interface timing (see figs 6 , 7 and 8) t cy(clk)(l3) l3clock time 500 -- ns t clk(l3)h l3clock high time 250 -- ns t clk(l3)l l3clock low time 250 -- ns t su(l3)a l3mode set-up time addressing mode 190 -- ns t h(l3)a l3mode hold time addressing mode 190 -- ns t su(l3)d l3mode set-up time data transfer mode 190 -- ns t h(l3)d l3mode hold time data transfer mode 190 -- ns t su(l3)da l3data set-up time data transfer and addressing mode 190 -- ns t h(l3)da l3data hold time data transfer and addressing mode 30 -- ns t stp(l3) l3mode halt time 190 -- ns
2000 jan 04 20 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T fig.9 serial interface timing. handbook, full pagewidth mgl721 t f t h(ws) t su(ws) t su(i)(d) t h(i)(d) t clkh(bit) t clkl(bit) t cy(clk)(bit) t r ws bck datai fig.10 system clock timing. handbook, full pagewidth mgr984 t sys t cwh t cwl
2000 jan 04 21 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 17 application information fig.11 application diagram. handbook, full pagewidth mgr983 UDA1328T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 2 3 1 28 27 26 25 24 23 22 21 20 19 18 17 vout3 agnd agnd agnd agnd dgnd vout4 v ssa vout5 vout6 vout3 vout4 vout5 vout6 v dda v dda n.c. test3 static static/l3 bck ws datai12 datai34 datai56 vout2p vout2n vout2 v ref vout1n vout1p test1 ds vout1 deem0 deem1 mute test2 v ddd v ddd v ssd l3data n.c. sysclk sysclk l3clock l3mode r13 100 w r14 10 k w c7 47 m f (16 v) c8 47 m f (16 v) c9 47 m f (16 v) c10 47 m f (16 v) r15 100 w r16 10 k w r17 100 w r18 10 k w agnd r19 100 w 1 w 47 w r20 10 k w 100 nf 100 m f (16 v) 1 w 100 nf 100 m f (16 v) dgnd agnd ground agnd c14 100 nf 100 pf 100 pf c13 47 m f (16 v) 47 m f 47 m f (16 v) (16 v) agnd 10 k w 10 k w 10 k w 10 k w 10 k w 10 k w 10 k w 10 k w 10 k w 10 k w 100 w 5 6 7 100 w agnd agnd agnd 1/2 ne5532 1/2 ne5532 dgnd v ddd v dda 100 m f (16 v) 100 m f (16 v) 3.3 v agnd bzn32a07
2000 jan 04 22 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 18 package outline unit a max. a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.10 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot287-1 mo-119 (1) 0.012 0.004 0.096 0.086 0.02 0.01 0.050 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w m b p d h e z e c v m a x a y 32 17 16 1 q a a 1 a 2 l p q detail x l (a ) 3 e pin 1 index 0 5 10 mm scale so32: plastic small outline package; 32 leads; body width 7.5 mm sot287-1 97-05-22 99-12-27
2000 jan 04 23 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 19 soldering 19.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 19.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 19.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 jan 04 24 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T 19.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 20 definitions 21 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
2000 jan 04 25 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T notes
2000 jan 04 26 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T notes
2000 jan 04 27 philips semiconductors preliminary speci?cation multi-channel ?lter dac UDA1328T notes
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